A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations.
Mingyu WangFang WangShaojun WeiZhaolin LiPublished in: Microelectron. J. (2016)
Keyphrases
- floating point
- high speed
- low power
- discrete cosine transform
- instruction set
- fast fourier transform
- sparse matrices
- fixed point
- low cost
- dct domain
- floating point arithmetic
- single chip
- image compression
- transform domain
- dct coefficients
- low power consumption
- real time
- power consumption
- discrete fourier transform
- frequency domain
- filter bank
- multiresolution