Low-power CMOS PLL for clock generator.
Wen-Chi WuChih-Chien HuangChih-Hsiung ChangNai-Heng TsengPublished in: ISCAS (1) (2003)
Keyphrases
- low power
- power consumption
- high speed
- cmos technology
- single chip
- power saving
- image sensor
- digital signal processing
- low power consumption
- high power
- low cost
- wireless transmission
- power management
- vlsi circuits
- logic circuits
- ultra low power
- power dissipation
- mixed signal
- delay insensitive
- signal processing
- image processing
- gate array
- vlsi architecture
- cmos image sensor
- nm technology
- real time