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A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS.

Xiongxin ZhaoZhixiang ChenXiao PengDajiang ZhouSatoshi Goto
Published in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2013)
Keyphrases
  • power consumption
  • low cost
  • circuit design
  • nm technology
  • cmos technology
  • low power consumption
  • ldpc codes
  • successive approximation