Stage-by-Stage Power Gating Circuit for Ultra-Low-Power Self-Timed Pipeline.

Shuji Sannomiya Kei Miyagi Makoto Iwata Hiroaki Nishikawa

Published in: PDPTA (2010)

Keyphrases

low power
high speed
power consumption
multiple stages
real time
data sets
neural network
real world
information retrieval
learning algorithm
video sequences
low cost
logic circuits