Low power delay locked loop with all digital controlled SAR delay cell.

Ko-Chi Kuo Chung-Yuan Chang Si-Hsien Li

Published in: APCCAS (2012)

Keyphrases

low power
power dissipation
power consumption
high speed
mixed signal
low cost
digital signal processing
vlsi circuits
single chip
high power
cmos technology
wireless transmission
logic circuits
vlsi architecture
low power consumption