Designing Low-Power and High-Speed FPGA-Based Binary Decision Tree Hardware Accelerators.

Roman Huzyuk Fanny Spagnolo Fabio Frustaci

Published in: AII (2022)

Keyphrases

low power
high speed
binary decision tree
power consumption
low cost
single chip
wireless transmission
high power
frame rate
application specific
digital signal processing
vlsi circuits
vlsi architecture
support vector machine
mixed signal
power dissipation
real time
power reduction
gate array