A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.
Atsushi KawasumiYasuhisa TakeyamaOsamu HirabayashiKeiichi KushidaFumihiko TachibanaYusuke NikiShinichi SasakiTomoaki YabePublished in: VLSIC (2012)