Model checking of MARTE/CCSL time behaviors using timed I/O automata.
Bo ChenXi LiXuehai ZhouPublished in: J. Syst. Archit. (2018)
Keyphrases
- model checking
- timed automata
- finite state machines
- temporal logic
- reachability analysis
- model checker
- formal verification
- finite state
- temporal properties
- automated verification
- formal specification
- partial order reduction
- verification method
- formal methods
- bounded model checking
- pspace complete
- computation tree logic
- symbolic model checking
- transition systems
- concurrent systems
- epistemic logic
- linear temporal logic
- asynchronous circuits
- planning domains
- process algebra
- petri net