Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems.
S. ElangoP. SampathPublished in: J. Circuits Syst. Comput. (2020)
Keyphrases
- ibm sp
- parallel computers
- graphics processing units
- parallel processing
- distributed memory machines
- efficient implementation
- parallel implementation
- distributed memory
- computer architecture
- hardware implementation
- highly parallel
- scientific computing
- low overhead
- pc cluster
- array processor
- hierarchical structure
- cluster of workstations
- higher level
- floating point
- genetic algorithm
- parallel distributed