A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC.
Masaki ToyokuraHisahi KodamaEiji MiyagoshiKoyoshi OkamotoMasahiro GionTakayuki MinemaruAkihiko OhtaniToshiyuki ArakiHiroshi TakenoToshihide AkiyamaBrent WilsonKunitoshi AonoPublished in: IEEE J. Solid State Circuits (1994)
Keyphrases
- pipeline architecture
- macroblock
- compressed video
- video coding
- motion jpeg
- bitstream
- video decoder
- inter frame
- video transcoding
- video codec
- bit rate
- rate distortion
- video coding standard
- motion estimation
- motion vectors
- video sequences
- compressed domain
- video signals
- coding efficiency
- video quality
- hardware implementation
- video compression
- motion compensation
- bit allocation
- motion compensated
- video transmission
- video encoder
- video streams
- transform domain
- reference frame
- video coder
- intra frame
- error propagation
- multimedia
- low bit rate
- digital video
- video data
- rate control
- coding scheme
- scalable video coding
- video content
- video encoding
- signal processing
- distributed video coding
- coding method
- video frames
- selection algorithm
- temporal correlation
- error concealment
- error resilience
- video analysis
- packet loss
- image quality
- compression efficiency
- intra prediction
- block size
- mode selection
- image sequences
- subband
- mode decision
- visual quality
- error resilient
- scalable video
- compression algorithm