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A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS.
Kuan-Chang Xavier Chen
William Wei-Ting Kuo
Azita Emami
Published in:
CICC (2020)
Keyphrases
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decision feedback
high speed
error propagation
multipath
soft decision
intersymbol interference
cmos technology
low power
low cost
bit error rate
silicon on insulator
metal oxide semiconductor
power consumption
channel estimation
hidden markov models
high resolution
multiscale