Programmable parallel coprocessor architectures for reconfigurable system-on-chip.
John WilliamsNeil W. BergmannPublished in: FPT (2004)
Keyphrases
- low cost
- massively parallel
- interconnection networks
- processor array
- hardware and software
- general purpose
- parallel architectures
- digital signal processors
- heterogeneous computing
- reconfigurable architecture
- parallel computing
- multi core processors
- parallel processing
- systolic array
- parallel computers
- embedded systems
- parallel implementation
- database
- fault tolerant
- parallel algorithm
- compute intensive
- field programmable gate array
- data flow
- power consumption
- image processing
- shared memory
- web services
- case study
- signal processing
- array processor
- coarse grain
- hardware implementation
- parallel computation
- processing units