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A low-noise, 8.95-11GHz all-digital frequency synthesizer with a metastability-free time-to-digital converter and a sleepy counter in 65nm CMOS.
Chen Jiang
Junren Liu
Yumei Huang
Zhiliang Hong
Published in:
ESSCIRC (2012)
Keyphrases
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high speed
circuit design
data conversion
control method
digital content