A Memory-Efficient Hardware Architecture for a Pulse Doppler Radar Vehicle Detector.
Sang-Dong KimJong-Hun LeePublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2011)
Keyphrases
- memory efficient
- hardware architecture
- radar signal
- signal processing
- hardware implementation
- pedestrian detection
- sar imaging
- received signal
- iterative deepening
- external memory
- hardware architectures
- field programmable gate array
- real time
- processing elements
- associative memory
- frequency modulation
- integral image
- inverse synthetic aperture radar
- multiple sequence alignment
- image processing algorithms
- pattern recognition
- image processing
- neural network
- synthetic aperture radar
- detection method
- detection algorithm
- data structure
- information systems