Towards sharing one FPGA SoC for both low-level PHY and high-level AI/ML computing at the edge.
Ioannis StratakosElissaios-Alexios PapatheofanousDimitrios DanopoulosGeorge LentarisDionysios I. ReisisDimitrios SoudrisPublished in: MeditCom (2021)
Keyphrases
- low level
- high level
- higher level
- artificial intelligence
- low level features
- middle level
- mid level
- visual information
- lower level
- maximum likelihood
- contour grouping
- high speed
- visual cues
- visual features
- object level
- hardware and software
- low power
- machine learning
- intelligent systems
- semantic information
- high level information
- ai systems
- intermediate level
- single chip
- verilog hdl
- john mccarthy
- hardware software co design
- higher level of abstraction
- fpga device
- expert systems
- hardware architecture
- parallel architecture
- field programmable gate array
- data acquisition
- knowledge sharing
- semantic concepts
- edge information
- hardware implementation
- signal processing