Parameterizable Ethernet Network-on-Chip Architecture on FPGA.

Helio Fernandes da Cunha Junior Bruno de Abreu Silva Vanderlei Bonato

Published in: DSD (2015)

Keyphrases

network on chip
multi processor
routing algorithm
software implementation
network simulator
packet switched
high speed
hardware architecture
hardware implementation
data acquisition
hardware design
real time
parallel architecture
single chip
program execution
low cost
multi core processors
distributed systems