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Scalable instruction set simulator for thousand-core architectures running on GPGPUs.
Shivani Raghav
Martino Ruggiero
David Atienza
Christian Pinto
Andrea Marongiu
Luca Benini
Published in:
HPCS (2010)
Keyphrases
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instruction set
floating point
application specific
computer architecture
embedded systems
level parallelism
ibm power processor
databases
query processing
memory access