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Scalable instruction set simulator for thousand-core architectures running on GPGPUs.

Shivani RaghavMartino RuggieroDavid AtienzaChristian PintoAndrea MarongiuLuca Benini
Published in: HPCS (2010)
Keyphrases
  • instruction set
  • floating point
  • application specific
  • computer architecture
  • embedded systems
  • level parallelism
  • ibm power processor
  • databases
  • query processing
  • memory access