Exploiting Timing Error Resilience in Processor Architecture.
John SartoriRakesh KumarPublished in: ACM Trans. Embed. Comput. Syst. (2013)
Keyphrases
- error resilience
- ibm power processor
- error propagation
- instruction set
- bitstream
- video coding
- packet loss
- video transmission
- distributed video coding
- high speed
- coding scheme
- video quality
- computer vision
- bit rate
- error concealment
- floating point
- compressed video
- memory access
- memory management
- transform domain
- power management
- channel coding
- macroblock
- power consumption
- computer simulation
- motion estimation
- optical flow
- multiscale