A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features.
Yesin RyuSung-Gi AhnJae Hoon LeeJaewon ParkYong-Ki KimHyochang KimYeong Geol SongHan-Won ChoSunghye ChoSeung Ho SongHaesuk LeeUseung ShinJonghyun AhnJe-Min RyuSuk Han LeeKyounghwan LimJungyu LeeJeong Hoan ParkJae-Seung JeongSunghwan JoDajung ChoSooyoung KimMinsu LeeHyunho KimMinhwan KimJae San KimJinah KimHyun Gil KangMyung-Kyu LeeSung-Rae KimYoung-Cheon KwonYoung-Yong ByunKijun LeeSangkil ParkJaeyoun YounMyeong-O. KimKyomin SohnSangJoon HwangJooYoung LeePublished in: IEEE J. Solid State Circuits (2023)