CORDIC arithmetic for an SVD processor.
Joseph R. CavallaroFranklin T. LukPublished in: IEEE Symposium on Computer Arithmetic (1987)
Keyphrases
- singular value decomposition
- high speed
- digital computer
- fpga implementation
- dimensionality reduction
- parallel processing
- arithmetic operations
- processor core
- multiprocessor systems
- instruction set
- memory management
- single chip
- floating point
- parallel architectures
- parallel architecture
- single processor
- parallel processors
- singular values
- dimension reduction
- low cost