An efficient hardware implementation of vector-based odd-even merge sorting.
Uday A. KoratPratik YadavHarshil ShahPublished in: UEMCON (2017)
Keyphrases
- hardware implementation
- signal processing
- efficient implementation
- software implementation
- hardware design
- image processing algorithms
- fpga implementation
- field programmable gate array
- dedicated hardware
- hardware architecture
- feature vectors
- memory management
- pipeline architecture
- real time
- information systems
- machine learning
- data mining