A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.

Kei-Yong Khoo Chao-Liang Chen Alan N. Willson Jr.

Published in: ISCAS (1) (1999)

Keyphrases

single phase
low power
circuit design
power supply
high speed
power consumption
power dissipation
low cost
data flow
image sensor
real time
input output
focal plane
mathematical model