An FPGA implementation of full-search variable block size motion estimation.
Shuichi AsanoZheng Zhi ShunTsutomu MaruyamaPublished in: FPT (2010)
Keyphrases
- fpga implementation
- variable block size motion estimation
- block size
- hardware implementation
- parallel architecture
- motion vectors
- variable block size
- motion estimation
- search range
- field programmable gate array
- video coding
- quadtree
- video coding standard
- bit rate
- motion compensation
- inter frame
- image processing algorithms
- block matching
- matching process
- reference frame
- signal processing
- video sequences
- computer vision
- video compression
- coding efficiency
- real time
- computational complexity
- image sequences
- digital images
- intra prediction
- data structure
- image processing