Maximally stateless model checking for concurrent bugs under relaxed memory models.
Alan HuangPublished in: ICSE (Companion Volume) (2016)
Keyphrases
- model checking
- temporal logic
- formal verification
- finite state machines
- reactive systems
- model checker
- temporal properties
- verification method
- formal specification
- finite state
- bounded model checking
- asynchronous circuits
- symbolic model checking
- computation tree logic
- linear temporal logic
- timed automata
- transition systems
- formal methods
- multi agent systems
- reachability analysis
- automated verification
- optimal solution