Level-2 cache for high performance /390 μ-processors.

H. Barsuhn W. Lochlein D. Wendel U. Wille P. Coppens

Published in: Microprocess. Microprogramming (1992)

Keyphrases

embedded processors
multithreading
memory subsystem
higher level
parallel algorithm
distributed memory
single chip
parallel implementation
parallel computing
coarse grained
multiprocessor systems
high efficiency