Reconfigurable hardware architecture for Mean Level and log-t CFAR detectors in FPGA implementations.
Jiafei ZhaoRongkun JiangHao YangXuetian WangHongmin GaoPublished in: IEICE Electron. Express (2019)
Keyphrases
- reconfigurable hardware
- low cost
- hardware software
- field programmable gate array
- hardware implementation
- software implementation
- functional units
- image processing
- evolvable hardware
- hardware and software
- hardware architectures
- hardware design
- processing elements
- fine grain
- efficient implementation
- multi core processors
- image processing algorithms
- data acquisition
- real time