Employing symmetry reductions in model checking.
A. Prasad SistlaPublished in: Comput. Lang. Syst. Struct. (2004)
Keyphrases
- model checking
- temporal logic
- formal verification
- finite state
- model checker
- automated verification
- temporal properties
- partial order reduction
- formal specification
- bounded model checking
- symbolic model checking
- formal methods
- computation tree logic
- verification method
- finite state machines
- reachability analysis
- transition systems
- epistemic logic
- concurrent systems
- process algebra
- satisfiability problem
- linear temporal logic
- alternating time temporal logic
- deterministic finite automaton
- asynchronous circuits
- knowledge base
- symmetry breaking
- modal logic
- petri net