Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs.
Carl IngemarssonPetter KallstromOscar GustafssonPublished in: FPL (2012)
Keyphrases
- digital signal processing
- signal processing
- field programmable gate array
- programmable logic
- fourier transform
- row column
- fast fourier transform
- hardware implementation
- systolic array
- frequency domain
- digital signal processors
- parallel architecture
- block wise
- relevant literature
- multiple valued
- efficient implementation
- high speed
- digital signal processor
- fourier domain
- image processing
- block size
- image blocks
- floating point
- embedded systems
- feature extraction
- coded images
- processing pipeline
- low power
- computational complexity
- fourier transformation
- pipeline architecture