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Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.
Jürgen Becker
Alexander Thomas
Maik Scheer
Published in:
VLSI-SoC (Selected Papers) (2003)
Keyphrases
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coarse grained
fine grained
instruction set
computation intensive
parallel architecture
systolic array
multithreading
linear array
shared memory
application specific
digital signal
high level
data flow
hardware implementation
low cost
protein sequences
general purpose
message passing
access control