Low-power Multiplier Optimized by Partial-Product Summation and Adder Cells.
Meng-Lin HsiaOscal T.-C. ChenPublished in: ISCAS (2009)
Keyphrases
- low power
- logic circuits
- power consumption
- low cost
- high speed
- power dissipation
- single chip
- high power
- wireless transmission
- floating point
- digital signal processing
- vlsi circuits
- cmos technology
- vlsi architecture
- low power consumption
- image sensor
- gate array
- data flow
- model based diagnosis
- real time
- hardware implementation
- image compression
- power reduction