Communication and Resource Deadlock Analysis Using IMDS Formalism and Model Checking.

Wiktor B. Daszczuk

Published in: Comput. J. (2017)

Keyphrases

model checking
temporal logic
formal verification
static analysis
model checker
pspace complete
finite state
formal methods
temporal properties
reachability analysis
automated verification
resource allocation
asynchronous circuits
transition systems
linear temporal logic
abstract interpretation