A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller.
Hongming ChenSong MaLiu WangHao ZhangKenyi PanYuhua ChengPublished in: Sci. China Inf. Sci. (2014)
Keyphrases
- low power
- low cost
- power consumption
- high speed
- mixed signal
- high power
- single chip
- power dissipation
- vlsi circuits
- control system
- real time
- wireless transmission
- low power consumption
- digital signal processing
- gate array
- vlsi architecture
- logic circuits
- cmos technology
- data flow
- packet loss
- control strategy
- signal processing
- image processing