Yet Another SHA-3 Round 3 FPGA Results Paper.
Brian BaldwinWilliam P. MarnanePublished in: IACR Cryptol. ePrint Arch. (2012)
Keyphrases
- high speed
- field programmable gate array
- real time image processing
- hardware implementation
- low cost
- verilog hdl
- fpga implementation
- hash functions
- low power consumption
- hardware architecture
- systolic array
- programmable logic
- software implementation
- real time
- signal processing
- fpga hardware
- single chip
- artificial intelligence
- evolutionary algorithm
- parallel hardware
- neural network
- dedicated hardware
- databases
- general purpose
- digital signal
- artificial neural networks
- data flow
- block cipher
- image processing
- hardware design
- genetic algorithm