Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications.
Kun ChenJingwen YangChunlei WuChen WangMin XuDavid Wei ZhangPublished in: IEEE Access (2023)
Keyphrases
- low power
- logic circuits
- low power consumption
- signal processor
- low cost
- power consumption
- high speed
- delay insensitive
- single chip
- wireless transmission
- high power
- digital signal processing
- vlsi architecture
- power reduction
- power dissipation
- vlsi circuits
- cmos technology
- image sensor
- real time
- application layer
- gate array