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Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications.
Kun Chen
Jingwen Yang
Chunlei Wu
Chen Wang
Min Xu
David Wei Zhang
Published in:
IEEE Access (2023)
Keyphrases
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low power
logic circuits
low power consumption
signal processor
low cost
power consumption
high speed
delay insensitive
single chip
wireless transmission
high power
digital signal processing
vlsi architecture
power reduction
power dissipation
vlsi circuits
cmos technology
image sensor
real time
application layer
gate array