The Acceleration of OPUS Codec Using Processor - FPGA Co-processing.
Sunny BezawadaBattu Prakash ReddyPublished in: VLSID (2023)
Keyphrases
- parallel architecture
- high speed
- real time
- general purpose processors
- hardware implementation
- real time image processing
- single chip
- low cost
- data acquisition
- systolic array
- parallel processors
- memory management
- processing elements
- image processing
- digital signal
- field programmable gate array
- data processing
- hardware architecture
- reconfigurable hardware
- frame rate
- low complexity
- gate array