FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics.
Shuja Ahmad Abbasi ZulhelmiAbdul Rahman M. AlamoudPublished in: IEICE Electron. Express (2015)
Keyphrases
- high speed
- low power
- single chip
- low power consumption
- design process
- real time
- digital signal processing
- gate array
- rapid prototyping
- computing systems
- simulation software
- hardware design
- simulation environment
- hardware implementation
- user interface
- computer science
- design space
- engineering design
- data acquisition
- hardware architecture
- mathematical model
- logic circuits
- case study