Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology.
Woo Joo KimSun Young HwangPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2008)
Keyphrases
- low power
- network topology
- vlsi architecture
- cmos technology
- low cost
- single chip
- low power consumption
- power consumption
- high speed
- mixed signal
- logic circuits
- digital signal processing
- power dissipation
- ad hoc networks
- vlsi circuits
- nm technology
- gate array
- ultra low power
- vlsi implementation
- design process
- network on chip
- cmos image sensor
- power reduction
- real time
- routing algorithm
- low complexity
- network structure