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A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS.
Xubin Chen
Xuan Li
Yupeng Shen
Jiarui Liu
Hua Chen
Published in:
IEICE Electron. Express (2019)
Keyphrases
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power consumption
analog to digital converter
high speed
domain specific
low cost
domain independent
bit vector
shift register
nm technology
infrared
domain experts
low power
silicon on insulator