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A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS.

Karim M. MegawerAhmed ElkholyDaniel CoombsMostafa Gamal AhmedAhmed ElmallahPavan Kumar Hanumolu
Published in: ISSCC (2018)
Keyphrases
  • power consumption
  • clock gating
  • low power
  • clock frequency
  • cmos technology
  • power reduction
  • nm technology
  • power dissipation
  • floating point
  • high speed
  • differential equations