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Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining.
Andreas Dielacher
Matthias Függer
Ulrich Schmid
Published in:
PODC (2009)
Keyphrases
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fault tolerant
distributed systems
fault tolerance
high speed
safety critical
load balancing
low cost
single chip
high assurance
expert systems
state machine
management system
high availability
computer systems
vlsi design
formal methods
mobile agents
vlsi implementation
evolvable hardware