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Design of Memory Access Module for YOLO v2 Neural Network Accelerator Based on FPGA.

Jun LiYing LiangShengkai WangJun Yang
Published in: EITCE (2020)
Keyphrases
  • neural network
  • verilog hdl
  • memory access
  • real time
  • low cost
  • design process
  • field programmable gate array
  • databases
  • management system
  • general purpose
  • operating system
  • computing systems
  • memory management