Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance.

Avijit Dutta Neil Tuttle Krishnan Anandh

Published in: ISQED (2013)

Keyphrases

hardware implementation
high speed
origin destination
hardware design
real time image processing
real time
randomly generated
field programmable gate array
low cost
shortest path
correlation coefficient
single chip
variance reduction
flow patterns
fpga technology
canonical form
training instances
prediction error