A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS.
Nathaniel J. AugustHyung-Jin LeeMartin VandepasRachael ParkerPublished in: ISSCC (2012)
Keyphrases
- power dissipation
- power consumption
- low power
- cmos technology
- nm technology
- user friendly
- low voltage
- vlsi circuits
- power reduction
- low cost
- silicon on insulator
- chip design
- power saving
- high speed
- logic circuits
- digital signal processing
- energy saving
- hardware and software
- flip flops
- mixed signal
- high frequency
- image processing
- power supply
- circuit design
- object oriented
- pattern recognition