Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic.
Benjamin SchrauwenJan M. Van CampenhoutPublished in: ESANN (2006)
Keyphrases
- hardware implementation
- pipelined architecture
- spiking neurons
- parallel architecture
- signal processing
- software implementation
- efficient implementation
- field programmable gate array
- image processing algorithms
- neuron model
- biologically plausible
- neural network
- learning algorithm
- parallel computing
- massively parallel