DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS.
Zhihong LuoGuoxing WangKhalil YousefBenjamin LauYong LianChun-Huat HengPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2018)
Keyphrases
- high speed
- cmos technology
- silicon on insulator
- power consumption
- nm technology
- np complete
- metal oxide semiconductor
- low cost
- low power
- packet loss
- propositional logic
- sat solvers
- first order logic
- analog vlsi
- power supply
- propositional satisfiability
- davis putnam
- root mean square
- constraint satisfaction
- theorem proving
- search space
- proof procedure
- ibm power processor
- np hard