Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs.
Yusuke KannoHiroyuki MizunoYoshihiko YasuKenji HiroseYasuhisa ShimazakiTadashi HoshiYujiro MiyairiToshifumi IshiiTetsuya YamadaTakahiro IritaToshihiro HattoriKazumasa YanagisawaNaohiko IriePublished in: IEEE J. Solid State Circuits (2007)
Keyphrases
- power distribution
- power consumption
- low power
- high power
- low cost
- high speed
- power reduction
- power management
- transmission line
- power saving
- low power consumption
- logic circuits
- vlsi architecture
- multithreading
- ultra low power
- cmos technology
- power dissipation
- signal processing
- wireless transmission
- energy dissipation
- nm technology