FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders.
David H. K. HoeL. P. Deepthi BollepalliChris D. MartinezPublished in: VLSI Design (2013)
Keyphrases
- fault tolerant
- bit parallel
- pipelined architecture
- fault tolerance
- state machine
- pattern matching
- parallel hardware
- multiple valued
- distributed systems
- programmable logic
- load balancing
- interconnection networks
- hardware implementation
- field programmable gate array
- data structure
- parallel implementation
- multi valued
- regular expressions
- parallel architecture
- high speed
- signal processing
- micron cmos
- computer architecture
- classical logic
- parallel computing
- low cost
- high availability
- parallel processing