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FPGA implementation of a low-power and area-efficient state-table-based compression algorithm for DSLR cameras.
Mohd Rafi Lone
Najeeb-ud-Din Hakim
Published in:
Turkish J. Electr. Eng. Comput. Sci. (2018)
Keyphrases
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low power
compression algorithm
power consumption
fpga implementation
low cost
high speed
image sensor
image compression
compression ratio
pattern recognition
hardware implementation
compression scheme
quadtree decomposition
real time
logic circuits
cmos technology
low bit rate
bitstream
high quality
computer vision