Low-Power Non-Binary LDPC Decoder Design via Adaptive Message Length Control Exploiting Domain-Specific Information.
Wenjie HuangLei WangPublished in: J. Signal Process. Syst. (2021)
Keyphrases
- low power
- low density parity check
- single chip
- low cost
- non binary
- low power consumption
- power consumption
- high speed
- logic circuits
- vlsi architecture
- ldpc codes
- power dissipation
- decoding algorithm
- gate array
- domain specific information
- cmos technology
- ultra low power
- error correction
- low complexity
- constraint satisfaction problems
- prior knowledge
- data sets
- hidden variables
- text mining
- data sources
- domain knowledge