FPGA parallel-pipelined AES-GCM core for 100G Ethernet applications.
Luca HenzenWolfgang FichtnerPublished in: ESSCIRC (2010)
Keyphrases
- parallel architecture
- high speed
- parallel hardware
- data acquisition
- shared memory
- hardware architectures
- hardware implementation
- systolic array
- parallel processing
- real time
- parallel implementation
- single processor
- low cost
- neural network
- parallel programming
- distributed memory
- parallel architectures
- software implementation
- low power
- linear array
- signal processing